The present invention relates to a semiconductor device.
An ADC, such as an SARADC (Successive Approximation Register Analog Digital Converter) and a pipeline ADC, has a DAC (Digital Analog Converter) in an inside thereof (W. Liu et al., “A 12b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” IEEE 2010 International Solid-State Circuits Conference, pp. 380-381, February 2010). Distortion of the DAC causes deterioration in accuracy of the whole ADC. There is a technique for realizing highly accurate conversion by calibration correction as the technique for countermeasures against the deterioration in accuracy. As one of these calibration techniques, there is a calibration technique in a digital domain which multiplies a digital code of the ADC by an appropriate weighting coefficient, and compensates for nonlinearity of the DAC. Japanese Unexamined Patent Application Publication No. 2012-44302 discloses as an ADC an A/D converter having cascaded plural MDACs.